The present invention relates generally to integrated circuits, and, more particularly, to a method and circuit that allow debugging of an integrated circuit.
Integrated circuits (IC) include various analog and digital circuits such as operational amplifiers, voltage regulators, voltage monitoring circuits, sensors, logic circuits, and non-volatile memories. When an IC is powered on, these circuits are reset, i.e., set to corresponding predefined states. A predefined state refers to a known and stable state. To facilitate the reset of the circuits, the IC includes a power-on-reset (POR) generator and a reset controller. The POR generator generates a POR signal to initiate a reset sequence. During the reset sequence, the reset controller initializes the aforementioned circuits to corresponding predefined states.
Generally, the reset sequence includes multiple reset phases. For example, an IC may have four reset phases (first through fourth). In the first reset phase (also referred as a POR phase), circuits such as voltage regulator circuits and voltage monitor circuits are initialized. The IC transitions to the second reset phase from one of the first reset phase, the third reset phase, the fourth reset phase, or an idle phase. The second reset phase is referred to as a clock initialization phase during which a clock signal is initialized, i.e., the IC receives a predefined minimum number of clock cycles of the clock signal from a clock signal source. Subsequently, the IC transitions from the second reset phase to the third reset phase. In the third reset phase, a non-volatile memory such as a flash memory is initialized to a known state. Further, configuration information such as factory settings and boot code in the non-volatile memory are accessed by a processor of the IC during the third reset phase. The IC transitions to the fourth reset phase from either the third reset phase or the idle phase. In the fourth reset phase, the circuits perform self-tests and a few of the circuits fetch and execute code from the non-volatile memory based on user requirements.
During the reset sequence multiple circuits are initialized. If any circuit is not initialized to a known state during the corresponding reset phase, the IC may remain in the reset phase. In such a scenario, the processor is not released from the reset sequence and the IC hangs. For example, in the first reset phase, if a voltage monitor circuit does not receive a voltage supply at a desired voltage level, then it may not de-assert and the IC will remain in the first reset phase. Similarly, in the second reset phase, if the clock signal is inappropriately initialized, an internal clock monitor circuit of the IC may not generate a clock-ok signal so there would be a failure of the clock signal initialization, holding the IC in the second reset phase. If the memory is inappropriately initialized in the third reset phase, the IC will remain in the third reset phase. As a result, the IC will be unable to transition to functional mode. Therefore, it is necessary to be able to debug the IC when the IC is hung in one of the reset phases. Moreover, there is a need to determine in which reset phase of the reset sequence the IC is held, and the signals that have caused the IC to be hung in the reset phase.
Existing debug circuits are inadequate for debugging the IC during the reset sequence. Further, it is undesirable to include dedicated debugging input/output (IO) pins because that would increase area and cost. Also, increase in the number of dedicated debugging IO pins limits the number of IO pins available for functional purposes. Furthermore, when the IC is stuck in the reset phase, the processor may be unable to initiate debugging. Hence, the control of debugging must be available to a user.
Therefore, it would be advantageous to have an IC that includes a debug circuit for debugging the IC during a reset sequence.